1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to a process for fabricating a T-shaped hard mask/conductor profile and a process of etching a self-aligned contact opening using a T-shaped hard mask/conductor profile to improve self-aligned contact isolation such as for a capacitor node.
2) Description of the Prior Art
In semiconductor fabrication, self-aligned contacts have gained wide use because they eliminate a photolithography step, increasing manufacturing efficiency and, more importantly, allowing for increased device density by eliminating the need for alignment alowances. A self-aligned contact is typically formed by fabricating spacers on the sidewalls of a conductive pattern (e.g. gate, bit line, etc) and on the sidewall of an overlying hard mask. The spacer, which can be composed of a dielectric, ussually silicon dioxide or silicon nitride provides electrical isolation between the contact and the conductive pattern.
As device density increases the horizontal spacing must decrease, and the thickness of the dielectric spacer must get smaller. As the dielectric spacer becomes smaller, the risk of bridging (forming a conductive path from the contact to the conductive pattern) increases. Leakage current also increases. As a result the performance and reliability of the semiconductor device is adversely effected.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following Patents.
U.S. Pat. No. 5,139,968 (Hayase et al.) teaches a method for forming a T-shaped gate electrode.
U.S. Pat. No. 5,407,870 (Okada et al.) discloses a process for forming a SiON layer.
U.S. Pat. No. 5,766,993 (Tseng) discloses a process for forming a poly gate and contact.